1. Field of the Invention
The present invention relates to unidirection threshold detectors such as Schmitt triggers and more particularly to Schmitt trigger circuits utilizing complementary metal oxide semiconductor (CMOS) technology.
2. Description of the Prior Art
A Schmitt trigger is a circuit that provides a digital output signal of either a logic HIGH or logic LOW state in response to the level of a supplied input signal. When the input signal crosses a respective one of an upper and lower threshold level, V.sub.H and V.sub.L, in a specified direction, the output level changes from a corresponding first of the LOW/HIGH logic states to the second. The logic states of the digital output signal can be represented by a variety of preselected signal attributes such as for example, by a binary set of voltage levels or current levels.
The basic operation of a Schmitt trigger is illustrated by reference to the hysteresis loop shown in FIG. 1. The output of a Schmitt trigger remains at a logic LOW while the level of an input signal V.sub.in remains in a first range a below the lower threshold level V.sub.L. When the input signal crosses the upper threshold level V.sub.H in an upwardly direction, as shown by the upwardly directed arrow c in FIG. 1, the output switches to the logic HIGH state. The output remains HIGH as long as the input signal remains in a second range d above the upper threshold level V.sub.H. If the input signal is reduced downwardly (f) to cross past the lower threshold level V.sub.L, the output switches back to the logic LOW state.
FIGS. 2A and 2B are respectively a block diagram and a schematic diagram of a previously known Schmitt trigger circuit 100. The circuit 100 comprises a pair of CMOS inverter stages, U1 and U2, that are arranged in a feedback configuration. The configuration includes respective input, intermediate, and output nodes; A, B and C. The first inverter U1 is formed of complementary n-channel and p-channel MOSFET's, N1 and P1. U1 is biased during a midpoint or output "neutral" switching phase of its operation by a neutral-point biasing current I.sub.o supplied from a voltage source +V.sub.DD through a pair of diode connected FET's, N3 and N4. The output of U1 switches between the logic LOW/HIGH states when an input voltage V.sub.in, applied to an input of the first inverter U1 through the input node A, is modulated from a first level below a neutral range of levels (including the switching midpoint) to a second level above the neutral range. The upper and lower limits of the neutral range are defined by the previously mentioned upper and lower threshold levels, V.sub.L and V.sub.H.
In order to drive the output of U1 (node B) LOW, the input voltage V.sub.in must exceed an upper threshold determining level V.sub.TH =V.sub.T1 +V.sub.T3 which is formed by summing a first threshold voltage V.sub.T3 belonging to the diode connected FET N3 and a second threshold voltage V.sub.T1 belonging the n-channel MOSFET N1. The threshold voltages, V.sub.T1 and V.sub.T3, are input voltages required by the first inverter U1 and the diode connected FET N3, respectively, for each to conduct a current having at least the magnitude of the neutral-point biasing current I.sub.o.
The input of the second inverter U2 is connected to the intermediate node B so as to be driven by the output of the first inverter U1. U2 produces an output voltage V.sub.out at the output node C. A switch SW1, which is formed an n-channel FET N5, is connected in parallel across N3 such that the switch SW1 will short the diode connected transistor N3 when the output node C goes HIGH. When the diode connected transistor N3 is shorted by the FET switch N5, the critical input voltage required for supporting the neutral-point biasing current I.sub.o switches from the upper threshold determining level, V.sub.TH =V.sub.T1 +V.sub.T3, to a lower threshold determining level, V.sub.TL =V.sub.T1 As a consequence, the turn-off/turn-on point of N1 is shifted to a lower level. N1 can therefore remain actively turned "on" to clamp the intermediate node B to the logic LOW state even when the input level V.sub.in falls under V.sub.TH =V.sub.T1 +V.sub.T3. N1 does not release the intermediate node B from the LOW state until V.sub.in drops to the lower threshold determining level V.sub.TL =V.sub.T1 or below.
The Schmitt trigger circuit 100 of FIGS. 2A and 2B has a number of drawbacks. The effective lower and upper threshold levels, V.sub.L and V.sub.H (FIG. 1), of the circuit 100 are not easily adjusted to conform to the voltage requirements of a specific logic design. For example, when a TTL (transistor-transistor-logic) circuit is to be used to drive the Schmitt trigger 100, the lower threshold voltage V.sub.L should be set to 0.8 volts and the upper threshold voltage V.sub.H should be set to 2.0 volts. A hysteresis gap of 1.2 volts between the upper and lower threshold levels is usually required in such circuits so that the Schmitt trigger will have a desired level of noise immunity. Unfortunately, this requirement is very difficult to realize with mass produced silicon chips built around CMOS technology. In such chips, if practical levels of output drive currents are to be realized over a wide range of fabrication process variations, V.sub.T3 must be nominally set to just above 1.0 volts and V.sub.T1 must also on average be set slightly greater than 1.0 volts. As a consequence, the average lower threshold voltage V.sub.L =V.sub.T3 of such mass produced IC's turns out to be significantly higher than 0.8 volts and the upper threshold voltage V.sub.H is on average substantially greater than 2.0 volts. The hysteresis gap is typically less than 1.2 volts so that desired levels of noise immunity cannot be obtained. The CMOS circuit 100 of FIGS. 2A and 2B is therefore generally incompatible with the requirements of other logic families such as the TTL family.
Another drawback of the circuit 100 is that the precise values of the upper and lower threshold levels, V.sub.H and V.sub.L, vary from one wafer processing batch to the next so that it is difficult to produce a desirable yield of chips having certain pre-selected threshold levels. The present invention overcomes the above drawbacks.